FIG. 1 shows a III-nitride compound semiconductor light emitting device according to the prior art. As shown in FIG. 1, the light emitting device comprises: a substrate 10; a buffer layer 11 epitaxially grown on the substrate 10; an n-type nitride semiconductor layer 12 epitaxially grown on the buffer layer 11, an active layer 13 epitaxially grown on the n-type nitride layer 12; a p-type nitride semiconductor layer 14 epitaxially grown on the active layer 13; a p-side electrode 17 formed on the p-type nitride semiconductor layer 14; a p-side bonding pad 15 formed on the p-side electrode 17; an n-side electrode 18 formed on the n-type nitride semiconductor layer 12 exposed by mesa-etching of at least the p-type nitride semiconductor layer 14 and the active layer 13; and a protection layer 16 formed on the p-side bonding pad 15, the p-side electrode 17 and the n-side electrode 18.
The substrate 10 can use a GaN-based substrate as a homogeneous substrate, and a sapphire substrate, a silicon carbide substrate or a silicon substrate as a heterogeneous substrate, but can use any other substrates on which nitride semiconductor layers can be grown.
The nitride semiconductor layers epitaxially grown on the substrate 10 are usually grown by means of MOCVD (Metal Organic Chemical Vapor Deposition) method.
The buffer layer 11 serves to reduce differences in lattice constant and the coefficient of thermal expansion between the heterogeneous substrate 10 and the nitride semiconductor. U.S. Pat. No. 5,122,845 discloses a technology in which an AlN buffer layer having a thickness of 100 A to 500 A is grown on a sapphire substrate at a temperature ranging from 380° C. to 800° C. U.S. Pat. No. 5,290,393 discloses a technology in which an Al(x)Ga(1-x)N (0≦x<1) buffer layer having a thickness of 10 Å to 5000 Å is grown on a sapphire substrate at a temperature ranging from 200° C. to 900° C. Korean Patent No. 10-0448352 discloses a technology in which a SiC buffer layer is grown at a temperature ranging from 600° C. to 990° C., and an In(x)Ga(1-x)N (0<x≦1) layer is grown on the SiC buffer layer.
In the n-type nitride semiconductor layer 12, at least a region (n-type contact layer) in which the n-side electrode 18 is formed is doped with an impurity. The n-type contact layer is preferably made of GaN and is doped with Si. U.S. Pat. No. 5,733,796 discloses a technology in which an n-type contact layer is doped with a desired doping concentration by controlling a mixing ratio of Si and other source materials.
The active layer 13 is a layer for emitting a photon (light) by recombination of electrons and holes, and is mainly made of In(x)Ga(1-x)N (0<x≦1). The active layer 13 is composed of a single quantum well or multi quantum wells. WO02/021121 discloses a technology in which only some of a plurality of quantum wells and barrier layers are doped.
The p-type nitride semiconductor layer 14 is doped with an impurity such as Mg, and has a p-type conductivity through an activation process. U.S. Pat. No. 5,247,533 discloses a technology in which a p-type nitride semiconductor layer is activated by means of irradiation of electron beam. U.S. Pat. No. 5,306,662 discloses a technology in which a p-type nitride semiconductor layer is activated through annealing at a temperature of 400° C. or more. Korean Patent No. 10-043346 discloses a technology in which NH3 and a hydrazine-based source material are used together as a nitrogen precursor for growing a p-type nitride semiconductor layer, so that the p-type nitride semiconductor layer has a p-type conductivity without an activation process.
The p-side electrode 17 serves to allow the current to be supplied to the entire p-type nitride semiconductor layer 14. U.S. Pat. No. 5,563,422 discloses a technology of a light-transmitting electrode, which is formed almost on the entire p-type nitride semiconductor layer, in ohmic contact with the p-type nitride semiconductor layer, and made of Ni and Au. U.S. Pat. No. 6,515,306 discloses a technology of a light-transmitting electrode made of ITO (Indium Tin Oxide), which is formed on the n-type superlattice layer formed on the p-type nitride semiconductor layer.
Meanwhile, the p-side electrode 17 can be formed to have such a thick thickness that the p-side electrode 17 does not transmit light, i.e., the p-side electrode 17 reflects light toward the substrate. A light emitting device using this p-side electrode 17 is called a flip chip. U.S. Pat. No. 6,194,743 discloses a technology of an electrode structure including an Ag layer of 20 nm or more in thickness, a diffusion barrier layer covering the Ag layer, and a bonding layer made of Au and Al, which covers the diffusion barrier layer.
P-side bonding pad 15 and n-side electrode 18 are for providing current into the device and for wire-bonding out of the device. U.S. Pat. No. 5,563,422 discloses a technology of an n-side electrode made of Ti and Al. U.S. Pat. No. 5,652,434 discloses a technology of p-side bonding pad directly contacted with p-type nitride semiconductor layer by partially removing the light-transmitting electrode.
One of unavoidable basic problems in the semiconductor light emitting device is that a phenomenon will occur where a significant portion of light generated in the semiconductor light emitting device is entrapped within the semiconductor light emitting device due to a difference in dielectric constant between the semiconductor light emitting device and the surrounding air. The material of a III-nitride semiconductor light emitting device also has a refractive index of about 2.5 which is 1.5 greater than a refractive index of 1 for the surrounding air. Due to this difference in refractive index, a significant portion of light emitted from the active layer of the III-nitride semiconductor light emitting device is entrapped and disappears as heat in the light emitting device. About 80% of light emitted from the active layer, as theoretically calculated, is entrapped and disappears in the light emitting device. To improve this light entrapment phenomenon is very important in that it can increase the external quantum efficiency of the light emitting device to maximize the output of the light emitting device.
In order to improve the external quantum efficiency, the chip configuration of the light emitting device is mechanically processed i the case of Cree Co. Also in some articles, the surface is made rough by a chemical etching or dry etching technique to improve the external quantum efficiency. Recently, the surface is also made rough by changing growth conditions, such as pressure, temperature and gas flow, in the growth of the p-type layer, while causing deterioration in the film quality. The above-mentioned mechanical processing is easy on a substrate, such as SiC, but almost impossible on a sapphire substrate with high strength. Also, the use of the chemical or dry etching technique has a limitation in area which can be made rough. Another problem is that the process becomes complicated since an etching process is further added to the existing LED (light emitting diode) process. Also, there are problems in the reproduction and uniformity of the etching process. Rather than methods requiring this additional process, it is preferable in view of a subsequent process to make the surface rough by changing growth conditions as described above. However, in the case of the method of making the surface rough by changing the growth conditions, the deterioration in the thin-film quality is unavoidable. Also, to achieve this improvement, a significantly thick layer must be formed. Accordingly, the growth of a layer with bad quality in more than certain thickness can increase the external quantum efficiency of the light emitting device, but cause a fatal problem in the reliability of the light emitting device.